1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming interconnects (i.e., conductors) with air gaps adjoining lateral surfaces of the interconnects to reduce capacitive coupling between adjacent interconnects employed by the integrated circuit.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed on the semiconductor topography and connected to contact areas thereon to form an integrated circuit. Building multi-level interconnect structures is well known in the art. Multi-level interconnect structures were developed as a result of continued shrinking of active devices combined with increasing area required to accommodate single-level interconnect structures. In fact, the area required to route single-level interconnect lines became greater than the area occupied by the active devices. Multi-level interconnect lines are more popular than single-level interconnect lines since the area required by multi-level interconnect lines is shared by several levels.
The semiconductor industry has devoted much effort to reducing the feature sizes of and the separation between adjacent structures, such as conductive interconnects or transistors, in integrated circuits. Reducing the size of structures employed by integrated circuits has resulted in many advantages, including higher circuit speed and increased complexity. This reduction in size, however, and the commensurate increase in density, have also given rise to problems, such as unwanted capacitive coupling between adjacent structures on the integrated circuit device. A change in the voltage applied to a conductor produces a change in charge distribution within the conductor. As the separation between conductors decreases, the charge distribution within one conductor may cause charge segregation within an adjacent, second conductor even in the absence of an applied voltage across the second conductor. As a result, current may undesirably flow through the second conductor, giving rise to a false signal (e.g., a logic 1 instead of a logic 0). Consequently, improper operation or failure of the integrated circuit device employing the conductors may occur.
A dielectric material known as an "interlevel dielectric" is generally used to isolate conductors arranged within a unitary level of an integrated circuit from each other and from structures configured within other levels. Unfortunately, the relative permittivity of the interlevel dielectric somewhat limits the minimum capacitive coupling that can be achieved between adjacent conductors. The permittivity .epsilon. of a material reflects the ability of the material to be polarized by an electric field. The capacitance between two layers of a conductive material separated by a dielectric is directly proportional to the permittivity of the dielectric. Typically, the permittivity of a material is described as its permittivity normalized to that of a vacuum, .epsilon..sub.0. The relative permittivity, or dielectric constant, .kappa., of a material is therefore defined as EQU .kappa.=.epsilon./.epsilon..sub.0
Silicon dioxide, with a dielectric constant of about 3.7-3.8, is often used as the interlevel dielectric. Adding fluorine to silicon dioxide or using an organic compound as the dielectric may produce materials with a dielectric constant lower than the dielectric constant of silicon dioxide without fluorine. In some cases, however, this reduction is still insufficient to eliminate capacitive coupling.
It would therefore be desirable to develop a technique for fabricating an integrated circuit with reduced capacitive coupling between adjacent conductors. A change in charge distribution within a first conductor would be less likely to cause charge segregation within a second conductor laterally spaced from the first conductor. Thus, unwanted current flow through the second conductor to undesirable places of the integrated circuit would be less likely to occur. As such, the integrated circuit would be more likely to function according to design. Furthermore, it would be beneficial if feature sizes of the integrated circuit could be reduced without concern over unwanted capacitive coupling. Therefore, reducing lateral capacitive coupling within an integrated circuit would allow for increased integration density and reduced propagation delay.